1. Field of the Invention
The present invention relates in general to a substrate voltage generation circuit for a semiconductor memory device, and more particularly to a composite mode substrate voltage generation circuit for a dynamic random access memory (referred to hereinafter as DRAM) in which a reference voltage for the generation of a substrate voltage in a self-refresh mode is lower than that in a normal refresh mode, so that a self-refresh operation can stably be performed at low power consumption, resulting in an increase in refresh efficiency of the DRAM.
2. Description of the Prior Art
Generally, a DRAM has operating modes such as a read mode, write mode, refresh mode, etc.. The refresh mode is classified into two modes, or a normal refresh mode and a self-refresh mode. The normal refresh mode is performed when the DRAM is normally operated, and the self-refresh mode is performed by a refresh counter in the DRAM when the DRAM is not accessed.
Because a memory cell access operation is not basically performed in the self-refresh mode, a self-refresh operation requires a period longer than that of a normal refresh operation. The self-refresh period depends on an interval for allowing charge stored in a memory cell not to be lost due to a leakage current.
In the DRAM, each memory cell is composed of one transistor and one capacitor. Charge stored in the capacitor may be lost due to a leakage current, which is generally classified into a junction leakage current at a storage node and a subthreshold leakage current in a subthreshold region of the transistor. Generally, as a semiconductor chip is highly integrated, a memory device becomes smaller in size and thus has a short channel effect. As a result, the subthreshold leakage current accounts for most charge losses in the DRAM cell.